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Block diagram of the Platform Controller Hub–based chipset architecture

The Platform Controller Hub (PCH) is a family of Intel microchips, introduced circa 2008. It is the successor to the previous Intel Hub Architecture, which used a northbridge and southbridge instead, and first appeared in the Intel 5 Series.

The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is only used when the chipset is required to support a processor with integrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCI-e lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge.

Overview[edit]

The PCH architecture supersedes Intel's previous Hub Architecture, with its design addressing the eventual problematic performance bottleneck between the processor and the motherboard. Over time, the speed of CPUs kept increasing but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, resulting in a performance bottleneck.

Under the Hub Architecture, a motherboard would have a two piece chipset consisting of a northbridge chip and a southbridge chip. As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge is now eliminated completely and its functions, the memory controller and PCI Express lanes for expansion cards, are now incorporated into the CPU die or package.

The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions. The system clock was previously a connection and is now fused in with the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is only used when the chipset requires supporting a processor with integrated graphics. The Intel Management Engine was also moved to the PCH starting with the Nehalem processors and 5-Series chipsets.

With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.

Ibex Peak[edit]

The Intel 5 Series chipsets were the first to introduce a PCH. This first PCH is codenamed Ibex Peak.

This has the following variations:

Issues[edit]

  • Bogus USB ports will be detected by desktop PCHs equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Applying AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12)
  • Bogus USB ports will be detected by mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Applying AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13)
  • Reading the HPET comparator timer immediately after a write returns the old value (erratum 14)
  • SATA 6Gbit/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)

Langwell[edit]

Langwell is the codename of a PCH in the Moorestown MID/smartphone platform.[1][2] for Atom Lincroft microprocessors.

This has the following variations:

  • AF82MP20 (PCH MP20)
  • AF82MP30 (PCH MP30)

Tiger Point[edit]

Tiger Point is the codename of a PCH in the Pine Trail netbook platform chipset for Atom Pineview microprocessors.

This has the following variations:

Topcliff[edit]

Topcliff is the codename of a PCH in the Queens Bay embedded platform chipset for Atom Tunnel Creek microprocessors.

It connects to the processor via PCI-E (vs. DMI as other PCHs do).

This has the following variations:

Cougar Point[edit]

Cougar Point is the codename of a PCH in Intel 6 Series chipsets for mobile, desktop, and workstation / server platforms. It is most closely associated with Sandy Bridge processors.

This has the following variations:

Issues[edit]

In the first month after Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered. Specifically, a transistor in the 3 Gbit/s PLL clocking tree was receiving too high voltage. The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and optical drives. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.[3][4]

Whitney Point[edit]

Whitney Point is the codename of a PCH in the Oak Trail tablet platform for Atom Lincroft microprocessors.

This has the following variations:

Panther Point[edit]

Panther Point is the codename of a PCH in Intel 7 Series chipsets for mobile and desktop. It is most closely associated with Ivy Bridge processors. These chipsets have integrated USB 3.0.[5]

This has the following variations:

Cave Creek[edit]

Cave Creek is the codename of the PCH most closely associated with Crystal Forest platforms and Gladden[6] or Sandy Bridge-EP/EN[7] processors.

  • DH8900 (PCH 8900) Communications
  • DH8903 (PCH 8903) Communications
  • DH8910 (PCH 8910) Communications
  • DH8920 (PCH 8920) Communications

Patsburg[edit]

Patsburg is the codename of a PCH in Intel 7 Series chipsets for server and workstation using the LGA 2011 socket. It was initially launched in 2011 as part of Intel X79 for the desktop enthusiast Sandy Bridge-E processors in Waimea Bay platforms.[8] Patsburg was then used for the Sandy Bridge-EP server platform (the platform was codenamed Romley and the CPUs codenamed Jaketown, and finally branded as Xeon E5-2600 series) launched in early 2012.[9]

Launched in the fall of 2013, the Ivy Bridge-E/EP processors (the latter branded as Xeon E5-2600 v2 series) also work with Patsburg, typically with a BIOS update.[10][11]

Patsburg has the following variations:

Coleto Creek[edit]

Coleto Creek is the codename of the PCH most closely associated with Highland Forest platforms and Ivy Bridge-EP[12] processors.

  • DH8925 (PCH 8925) Communications
  • DH8926 (PCH 8926) Communications
  • DH8950 (PCH 8950) Communications
  • DH8955 (PCH 8955) Communications

Lynx Point[edit]

Lynx Point is the codename of a PCH in Intel 8 Series chipsets, most closely associated with Haswell processors with LGA 1150 socket.[13] The Lynx Point chipset connects to the processor primarily over the Direct Media Interface (DMI) interface.[14]

The following variants are available:[15]

In addition the following newer variants are available, additionally known as Wildcat Point, which also support Haswell Refresh processors:[16]

  • DH82H97 (PCH H97) Desktop Home
  • DH82Z97 (PCH Z97) Combined desktop base and home

Issues[edit]

A design flaw causes devices connected to the Lynx Point's integrated USB 3.0 controller to be disconnected when the system wakes up from the S3 state (Suspend to RAM), forcing the USB devices to be reconnected although no data is lost.[17][18] This issue is corrected in C2 stepping level of the Lynx Point chipset.[19]

Wellsburg[edit]

Wellsburg is the codename for the C610-series PCH, supporting the Haswell-E (Core i7 Extreme), Haswell-EP (Xeon E5-16xx v3 and Xeon E5-26xx v3), and Broadwell-EP (Xeon E5-26xx v4) processors. Generally similar to Patsburg, Wellsburg consumes only up to 7 W when fully loaded.[20]

Wellsburg has the following variations:

  • DH82029 (PCH C612), intended for servers and workstations
  • DHX99 (PCH X99), intended for workstations

See also[edit]

References[edit]

  1. ^ Langwell Background Information, Intel, retrieved 2010-08-03 
  2. ^ New Intel Atom Processor-Based Platform Using Significantly Lower Power Readies Intel for Smartphone, Tablet Push, Intel, May 4, 2010, retrieved 2010-07-27 
  3. ^ Intel Identifies Chipset Design Error, Implementing Solution, Intel, 31 January 2011 
  4. ^ The Source of Intel's Cougar Point SATA Bug, AnandTech, 31 January 2011 
  5. ^ "Correction: Ivy Bridge and Thunderbolt - Featured, not Integrated". AnandTech. Retrieved 2014-01-21. 
  6. ^ (2:48) (2014-01-13). "Intel Xeon/Core/Pentium/Celeron, Communications Chipset 89xx". Intel. Retrieved 2014-01-21. 
  7. ^ "Intel Xeon Processor E5-2600/E5-2400/Communications Chipset 89xx". Ssl.intel.com. Retrieved 2014-01-21. 
  8. ^ "A Look Into Intel's Next Gen Enthusiast Platform : Sandy Bridge E & Waimea Bay", vr-zone.com, April 15, 2010, retrieved 2010-07-27 [dead link]
  9. ^ "Intel plugs both your sockets with 'Jaketown' Xeon E5-2600s • The Channel". Channelregister.co.uk. 2012-03-06. Retrieved 2014-01-21. 
  10. ^ "Ivy Bridge-E Not a Cut-down 8-core, 20 MB LLC Die". techPowerUp.com. 2013-08-12. Retrieved 2014-01-21. 
  11. ^ http://www.theregister.co.uk/2013/09/10/intel_ivy_bridge_xeon_e5_2600_v2_launch/
  12. ^ "Intel Announces Highland Forest, a New Platform that will Accelerate Network Transformation". Intel. 2013-12-04. Retrieved 2014-08-09. 
  13. ^ Shawn Knight (2012-11-13). "Leaked Intel slides detail Haswell's Lynx Point chipset". techspot.com. Retrieved 2013-10-30. 
  14. ^ "Intel "Lynx Point" 8-series Chipset Detailed, Completely SATA 6 Gbit/s". techpowerup.com. 2012-02-17. Retrieved 2013-10-30. 
  15. ^ "Products (Formerly Lynx Point)". Intel. Retrieved 2013-10-30. 
  16. ^ Andrew Cunningham (2014-05-11). "New Intel chipsets speed up your storage, but they’re missing new CPUs". arstechnica.com. Retrieved 2014-05-13. 
  17. ^ "Lynx Point USB 3.0 Controller Issue Correction Needs New Hardware". techpowerup.com. 2013-03-11. Retrieved 2013-10-30. 
  18. ^ Frank Everaardt (2013-03-01). "USB 3.0 problems for Intel's Haswell". hardware.info. Retrieved 2013-10-30. 
  19. ^ "Haswell C2 stepping availability". arstechnica.com. 2013. Retrieved 2013-10-30. 
  20. ^ "Intel Readies 18-Core Xeon "Broadwell-EP" Microprocessors for Launch in 2015 – Report". xbitlabs.com. Retrieved 2014-01-21. 

Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Platform_Controller_Hub — Please support Wikipedia.
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Mon, 10 Aug 2015 05:56:15 -0700

A typical Intel desktop processor requires a second, external chip known as a "platform controller hub." With how Intel does things today, the "mainstream" desktop platforms have their own platform controller hubs (these are generally also used for ...

EE Times

EE Times
Wed, 05 Aug 2015 16:22:35 -0700

The rest of the Skylake family, along with the Intel 100 Series chipset (codenamed Sunrise Point) as well as complete system-on-chip (SoC) versions using a new Platform Controller Hub (PCH) on the die of Skylake's H, U, Y and Xeon variants are said be ...

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Sun, 09 Aug 2015 01:03:45 -0700

PCI Express-based SSDs are nothing new; OCZ, Plextor and Asus all released disks in 2013 and 2014, but because they all used similar two-lane, PCIe 2.0 controllers, the speed advantages over traditional SATA3 SSDs weren't enough to justify the much ...

Tom's Hardware

Tom's Hardware
Mon, 24 Aug 2015 08:56:15 -0700

... decodifica della compressione. La piattaforma su cui troveranno spazio queste CPU avrà un PCH (Platform Controller Hub) chiamato Lewisburg, collegato al processore tramite quattro linee DMI 3.0. La piattaforma sarà in grado di scalare fino a otto ...

Motley Fool

Motley Fool
Wed, 17 Jun 2015 09:45:30 -0700

And, although Intel will move away from the 32-nanometer technology for the platform controller hub on the company's upcoming Skylake PC processors, the 32-nanometer technology isn't quite done yet. The platform controller hub required to power Intel's ...

Motley Fool

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Tue, 12 May 2015 11:07:12 -0700

Instead, I believe Intel is integrating these features into the platform controller hub or "PCH," that resides on the same package as the main processor die, as the slide below suggests. Pch Reuse. On the left is the Skylake PCH. On the right is ...

Dispatch Times

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Mon, 27 Jul 2015 05:22:30 -0700

In terms of power consumption, Intel claims that total silicon solution power (which includes the CPU, the platform controller hub, the Wi-Fi and wired networking chips) is as much as 80% lower. Then, for desktop processors (S-series), Intel claims ...

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The real issue with M.2 is that on Intel systems it's generally implemented behind the PCH (Platform Controller Hub), which features only Gen 2 PCIe. That's because the PCH lies behind the DMI (Direct Media Interface) which is capped at 2GBps. You can ...
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