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Block diagram of the Platform Controller Hub–based chipset architecture

The Platform Controller Hub (PCH) is a family of Intel microchips, introduced circa 2008. It is the successor to the previous Intel Hub Architecture, which used a northbridge and southbridge instead, and first appeared in the Intel 5 Series.

The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is only used when the chipset is required to support a processor with integrated graphics. As such, I/O Functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCI-e lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge.


The PCH architecture supersedes Intel's previous Hub Architecture based architecture, and is designed to address the eventual problem of a bottleneck between the processor and the motherboard. The speed of CPU kept increasing, but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, thus a bottleneck would occur.

Under the hub architecture, a motherboard would have a two piece chipset consisting of a northbridge chip and a southbridge chip. As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge is now eliminated completely and its functions, the integrated memory controller (IMC) and graphics lanes, are now incorporated into the CPU die or package.

The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions. The system clock was previously a connection and is now fused in with the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is only used when the chipset requires supporting a processor with integrated graphics. The Intel Management Engine was also moved to the PCH starting with the Nehalem processors and 5-Series chipsets.

With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.

Ibex Peak[edit]

The Intel 5 Series chipsets were the first to introduce a PCH. This first PCH is codenamed Ibex Peak.

This has the following variations:


  • Bogus USB ports will be detected at desktop PCH equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Adding AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12)
  • Bogus USB ports will be detected at mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Adding AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13)
  • Reading the HPET comparator timer immediately after a write, returns the old value (erratum 14)
  • SATA 6Gbit/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)


Langwell is the codename of a PCH in the Moorestown MID/smartphone platform.[1][2] for Atom Lincroft microprocessors.

This has the following variations:

  • AF82MP20 (PCH MP20)
  • AF82MP30 (PCH MP30)

Tiger Point[edit]

Tiger Point is the codename of a PCH in the Pine Trail netbook platform chipset for Atom Pineview microprocessors.

This has the following variations:


Topcliff is the codename of a PCH in the Queens Bay embedded platform chipset for Atom Tunnel Creek microprocessors.

It connects to the processor via PCI-E (vs. DMI as other PCHs do).

This has the following variations:

Cougar Point[edit]

Cougar Point is the codename of a PCH in Intel 6 Series chipsets for mobile, desktop, and workstation / server platforms. It is most closely associated with Sandy Bridge processors.

This has the following variations:


In the first month of Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered. Specifically, a transistor in the 3 Gbit/s PLL clocking tree was receiving too high voltage. The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and DVD drives. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.[3][4]

Whitney Point[edit]

Whitney Point is the codename of a PCH in the Oak Trail tablet platform for Atom Lincroft microprocessors.

This has the following variations:

Panther Point[edit]

Panther Point is the codename of a PCH in Intel 7 Series chipsets for mobile and desktop. It is most closely associated with Ivy Bridge processors. These chipsets have integrated USB 3.0.[5]

This has the following variations:

Cave Creek[edit]

Cave Creek is the codename of the PCH most closely associated with Crystal Forest platforms and Gladden[6] or Sandy Bridge-EP/EN[7] processors.

  • DH8900 (PCH 8900) Communications
  • DH8903 (PCH 8903) Communications
  • DH8910 (PCH 8910) Communications
  • DH8920 (PCH 8920) Communications


Patsburg is the codename of a PCH in Intel 7 Series chipsets for server and workstation using the LGA 2011 socket. It was initially launched in 2011 as part of Intel X79 for the desktop enthusiast Sandy Bridge-E processors in Waimea Bay platforms.[8][dead link] Patsburg was then used for the Sandy Bridge-EP server platform (the platform was codenamed Romley and the CPUs codenamed Jaketown, and finally branded as Xeon E5-2600 series) launched in early 2012.[9]

Launched in the fall of 2013, the Ivy Bridge-E/EP processors (the latter branded as Xeon E5-2600 v2 series) also work with Patsburg, typically with a BIOS update.[10][11]

Patsburg has the following variations:

Lynx Point[edit]

Lynx Point is the codename of a PCH in Intel 8 Series chipsets, most closely associated with Haswell processors with LGA 1150 socket.[12] The Lynx Point chipset connects to the processor primarily over the Direct Media Interface (DMI) interface.[13]

The following variants are available:[14]


A design flaw causes devices connected to the Lynx Point's integrated USB 3.0 controller to be disconnected when the system wakes up from the S3 state (Suspend to RAM), forcing the USB devices to be reconnected although no data is lost.[15][16] This issue is corrected in C2 stepping level of the Lynx Point chipset.[17]


Due to launch in 2014, Wellsburg is the codename for the C610 series PCH, planned for the Haswell-EP (Xeon E5-2600 v3) and Broadwell-EP (Xeon E5-2600 v4) processors. Generally similar to Patsburg, Wellsburg is supposed to consume only 7 W, fully loaded.[18]

See also[edit]


  1. ^ Langwell Background Information, Intel Corporation, retrieved 2010-08-03 
  2. ^ New Intel Atom Processor-Based Platform Using Significantly Lower Power Readies Intel for Smartphone, Tablet Push, Intel Corporation, May 4, 2010, retrieved 2010-07-27 
  3. ^ Intel Identifies Chipset Design Error, Implementing Solution, Intel, 31 January 2011 
  4. ^ The Source of Intel's Cougar Point SATA Bug, AnandTech, 31 January 2011 
  5. ^ "Correction: Ivy Bridge and Thunderbolt - Featured, not Integrated". AnandTech. Retrieved 2014-01-21. 
  6. ^ (2:48) (2014-01-13). "Intel® Xeon®/Core™/Pentium®/Celeron®, Communications Chipset 89xx". Ssl.intel.com. Retrieved 2014-01-21. 
  7. ^ "Intel® Xeon® Processor E5-2600/E5-2400/Communications Chipset 89xx". Ssl.intel.com. Retrieved 2014-01-21. 
  8. ^ A Look Into Intel's Next Gen Enthusiast Platform : Sandy Bridge E & Waimea Bay, VR-Zone, April 15, 2010, retrieved 2010-07-27 
  9. ^ "Intel plugs both your sockets with 'Jaketown' Xeon E5-2600s • The Channel". Channelregister.co.uk. 2012-03-06. Retrieved 2014-01-21. 
  10. ^ "Ivy Bridge-E Not a Cut-down 8-core, 20 MB LLC Die". techPowerUp. 2013-08-12. Retrieved 2014-01-21. 
  11. ^ http://www.theregister.co.uk/2013/09/10/intel_ivy_bridge_xeon_e5_2600_v2_launch/
  12. ^ Shawn Knight (2012-11-13). "Leaked Intel slides detail Haswell's Lynx Point chipset". techspot.com. Retrieved 2013-10-30. 
  13. ^ "Intel "Lynx Point" 8-series Chipset Detailed, Completely SATA 6 Gb/s". techpowerup.com. 2012-02-17. Retrieved 2013-10-30. 
  14. ^ "Products (Formerly Lynx Point)". intel.com. Retrieved 2013-10-30. 
  15. ^ "Lynx Point USB 3.0 Controller Issue Correction Needs New Hardware". techpowerup.com. 2013-03-11. Retrieved 2013-10-30. 
  16. ^ Frank Everaardt (2013-03-01). "USB 3.0 problems for Intel's Haswell". hardware.info. Retrieved 2013-10-30. 
  17. ^ "Haswell C2 stepping availability". arstechnica.com. 2013. Retrieved 2013-10-30. 
  18. ^ "Intel Readies 18-Core Xeon “Broadwell-EP” Microprocessors for Launch in 2015 – Report". X-bit labs. Retrieved 2014-01-21. 

Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Platform_Controller_Hub — Please support Wikipedia.
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