digplanet beta 1: Athena
Share digplanet:

Agriculture

Applied sciences

Arts

Belief

Business

Chronology

Culture

Education

Environment

Geography

Health

History

Humanities

Language

Law

Life

Mathematics

Nature

People

Politics

Science

Society

Technology

The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography

References[edit]

  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).

Other[edit]


Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Planar_process — Please support Wikipedia.
This page uses Creative Commons Licensed content from Wikipedia. A portion of the proceeds from advertising on Digplanet goes to supporting Wikipedia.
56068 videos foundNext > 

Fairchild Briefing on Integrated Circuits

[Recorded: October, 1967] This half hour color promotional/educational film on the integrated circuit was produced and sponsored by Fairchild Semiconductor C...

Planar Technology. D-Pak Features

Planar Technology. D-Pak Features. The planar technology combines a number of process operations to fabricate semiconductor devices with p-n junctions. P-n b...

Building the Future: The Planar Integrated Circuit

[Recorded: May 8, 2009] The solid circuits built originally by Jack Kilby established that all the components required to make general-purpose electronic cir...

Understanding The FinFet Semiconductor Process

This video has been updated and the new version can be viewed at the link below. http://youtu.be/YYDNG4crRCs Threshold Systems provides consulting services t...

The assembly process uses planar fabrication methods to make assembly fast and easy

The assembly process uses planar fabrication methods to make assembly fast and easy. Fabrication requires a solid ink printer, a ferric chloride etch tank, a...

Introduction to Planar Mapping (Projection) with Autodesk Maya

Level: Beginner This video demos the basics of UV mapping with planar projection technique, whereby it is a process about how to wrap a 2d texture image onto...

Tutorial: Digital makeup with mocha Pro planar tracking

Adding digital makeup and improving skin wrinkes & blemishes can be a timely process. In this video tutorial, Imagineer Systems Product Manager, Martin Brenn...

The Legacy of Fairchild Semiconductor

[Recorded Oct 5, 2007] Founded in September 1957 in Palo Alto, California by eight young engineers and scientists from Shockley Semiconductor Laboratories, F...

Build technique for 5.8GHz CP antennas (Cloverleaf or Skew-Planar Wheel)

This is the way I have been building my Cloverleaf and Skew-Planar antennas. I have no idea if this is actually a good way of building them. What I knwo is t...

Planar Roughing from Solid Models with SmartCAM V17

An all new process for automated roughing toolpath generation directly from a solid model is introduced in SmartCAM V17. The new Planar Rough process generat...

56068 videos foundNext > 

109 news items

 
EE Journal
Tue, 24 Feb 2015 08:58:32 -0800

That means that these families are based on TSMC's 16nm FinFET process - rather than the 20nm planar process that the current “UltraScale” devices use. And, since we're on the topic of underlying fabrication process and FinFETs, let's get that part of ...
 
Fudzilla (blog)
Fri, 27 Feb 2015 00:37:30 -0800

The company announced the oversized GPU yesterday, with some truly impressive performance claims – the GT7900 trounces the Xbox 360 and PlayStation 3 GPUs in sheer GFLOPs, and even pulls ahead of Nvidia's GT 730M.

GSMArena.com

GSMArena.com
Sun, 15 Feb 2015 23:28:33 -0800

Samsung has announced the industry first chip based on 14nm 3D FinFET processor. This is a marked improvement over the 20nm planar process used to manufacture the current generation Exynos 7 processor. According to Samsung, the new Exynos 7 ...
 
Seeking Alpha (registration)
Mon, 23 Feb 2015 06:55:26 -0800

For example, there's nothing 22nm in Intel's so-named process, or anything 20nm in TSMC's (NYSE:TSM) planar process, although they do try to convey some meaning about the general characteristics of the technology. So, although Samsung (OTC:SSNLF) ...
 
Tom's Hardware
Wed, 18 Feb 2015 12:28:55 -0800

The surprisingly fast release of Cortex-A72 chips, along with "midrange" branding for the 618 and 620, comes mainly as a consequence of building these chips on the old 28nm planar process (according to a Qualcomm spokesperson), rather than the ...
 
EE Times
Wed, 21 Sep 2011 07:03:23 -0700

The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density. Paper 15.1, Bulk ...

FrazPC.pl

FrazPC.pl
Wed, 18 Feb 2015 23:06:50 -0800

The surprisingly fast release of Cortex-A72 chips, along with "midrange" branding for the 618 and 620, comes mainly as a consequence of building these chips on the old 28nm planar process (according to a Qualcomm spokesperson), rather than the ...

ZDNet

ZDNet
Thu, 02 Oct 2014 13:12:03 -0700

The two companies said that 14nm chips will be up to 15 percent smaller than those manufactured on a 20nm planar process, while TSMC's 16nm FinFET process will deliver no scaling benefit over 20nm. The move also provides a second source for 14nm ...
Loading

Oops, we seem to be having trouble contacting Twitter

Support Wikipedia

A portion of the proceeds from advertising on Digplanet goes to supporting Wikipedia. Please add your support for Wikipedia!

Searchlight Group

Digplanet also receives support from Searchlight Group. Visit Searchlight