The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.
The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.
The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.
Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography. Some researchers use even higher-energy extreme ultraviolet lithography
Understanding The FinFet Semiconductor Process
This video has been updated and the new version can be viewed at the link below. http://youtu.be/YYDNG4crRCs Threshold Systems provides consulting ...
Building the Future: The Planar Integrated Circuit
[Recorded: May 8, 2009] The solid circuits built originally by Jack Kilby established that all the components required to make general-purpose electronic circuits ...
Fairchild Briefing on Integrated Circuits
[Recorded: October, 1967] This half hour color promotional/educational film on the integrated circuit was produced and sponsored by Fairchild Semiconductor ...
Planar Technology. D-Pak Features
Planar Technology. D-Pak Features. The planar technology combines a number of process operations to fabricate semiconductor devices with p-n junctions.
The Legacy of Fairchild Semiconductor
[Recorded Oct 5, 2007] Founded in September 1957 in Palo Alto, California by eight young engineers and scientists from Shockley Semiconductor Laboratories, ...
The assembly process uses planar fabrication methods to make assembly fast and easy
The assembly process uses planar fabrication methods to make assembly fast and easy. Fabrication requires a solid ink printer, a ferric chloride etch tank, ...
Tutorial: Digital makeup with mocha Pro planar tracking
Adding digital makeup and improving skin wrinkes & blemishes can be a timely process. In this video tutorial, Imagineer Systems Product Manager, Martin ...
BGA Planar CT (process)
Introduction to Planar Mapping (Projection) with Autodesk Maya
Level: Beginner This video demos the basics of UV mapping with planar projection technique, whereby it is a process about how to wrap a 2d texture image onto ...
Two Link Planar Simulation for Forward Kinematics using Processing
Two Link Planar Simulation for Forward Kinematics using Processing.
Thu, 23 Jul 2015 08:49:40 -0700
GlobalFoundries claims that with this approach it can produce chips that deliver better performance and lower power than the commonly-used 28nm planar process at a comparable cost (and much lower cost than 14nm FinFETs, which require many more ...
Wed, 22 Jul 2015 20:24:20 -0700
To deal with today's most powerful mobile chips' power consumption you need manufacture it with expensive 20nm planar process or even more expensive 14/16nm FinFET (comparing to 28nm planar) to prevent overheating. Check out how many times ...
Wed, 29 Apr 2015 23:46:01 -0700
United Microelectronics Corp., the world's second largest contract maker of semiconductors, said that it would not offer 20nm planar fabrication process, but will jump directly to 16nm FinFET manufacturing technology. Skipping the node will help the ...
Sat, 19 Oct 2013 00:17:28 -0700
AMD may not have its own foundry, exactly, but it did essentially found Globalfoundries. Thus, it has some control over when and how its process technologies advance. Over the next 2 quarters, the 14nm FinFET and 20nm planar process technologies should ...
Wed, 21 Sep 2011 07:03:23 -0700
The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density. Paper 15.1, Bulk ...
Mon, 22 Jun 2015 06:47:22 -0700
Advanced Fabrication: The new processors comprise over 128,000 Josephson junctions (tunnel junctions with superconducting electrodes) in a 6-metal layer planar process with 0.25µm features, believed to be the most complex superconductor integrated ...
Tue, 24 Feb 2015 08:58:32 -0800
That means that these families are based on TSMC's 16nm FinFET process - rather than the 20nm planar process that the current “UltraScale” devices use. And, since we're on the topic of underlying fabrication process and FinFETs, let's get that part of ...
Mon, 06 Apr 2015 10:34:44 -0700
Like the Snapdragon 810, the Apple A8 (iPhone 6 and iPhone 6 Plus) and A8X (iPad Air 2) are made by TSMC on its 20nm planar process. But Samsung may have won back much of Apple's business on the A9 because of its lead on FinFETs. More Surface 3.
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