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The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography

References[edit]

  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).

Other[edit]


Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Planar_process — Please support Wikipedia.
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6 news items

 
SemiAccurate
Thu, 17 Apr 2014 09:07:30 -0700

It has a claimed “up to” 20% higher speed, 30% less power used, and 15% less area than the 20nm planar process that it replaces the transistors for. Please do note that this is marketing speak for pick one of the three and maybe not even that even ...
 
PC Perspectives
Tue, 08 Apr 2014 18:28:46 -0700

Exactly how big the mentioned gains will be will depend on the specific manufacturing process, with smaller gains from a bulk/planar process shrink or greater improvements coming from more advanced methods such as FD-SOI if the new chip on a 20nm ...
 
Seeking Alpha
Wed, 02 Apr 2014 11:56:15 -0700

Naww, everyone knows that TSMC (TSM) has the Apple business with their wonderful 20nm planar process, right? Of course, TSMC was a big help in the Apple memory problem and should be paid off for that...yeah, right. I just love it when a plan comes ...
 
EE Times
Wed, 19 Mar 2014 15:09:36 -0700

In a paper at the IEEE International Interconnect Technology Conference in San Jose, GlobalFoundries will describe a middle-of-line (MoL) chip stack in a 20 nm planar process, which achieves a "near-zero" keep-out zone around its TSVs. Prior work used ...
 
PR Newswire (press release)
Wed, 26 Mar 2014 02:56:15 -0700

... generation of products that are smaller, require less power and run faster. A recent TSMC report suggests that 16nm FinFET technology will achieve 55% power reduction and 35% higher speed as compared to the standard 28nm HK/MG planar process.

Eetasia.com (subscription)

Eetasia.com (subscription)
Thu, 20 Mar 2014 01:58:27 -0700

The company will describe a middle-of-line (MoL) chip stack in a 20nm planar process that achieves a "near-zero" keep-out zone around its TSVs in a paper at the IEEE International Interconnect Technology Conference in May. Prior work used keep-out ...
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