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The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography

References[edit]

  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).

Other[edit]


Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Planar_process — Please support Wikipedia.
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Seeking Alpha
Fri, 10 Apr 2015 06:30:00 -0700

Global Foundries and Samsung (OTC:SSNLF) have begun ramping their own 14nm FinFET process for customers as of earlier this month, and TSMC debuted its 20nm planar process back in September with Apple's (NASDAQ:AAPL) iPhone 6. The fabs may ...
 
ElectronicsWeekly.com
Fri, 10 Apr 2015 07:48:45 -0700

At that time, advances were adopted quickly and widely – Jean Hoerni's planar process revolutionised the IC industry. By 1964, 75% of the semiconductor industry were using the planar process, but fewer than ten companies had actually licensed it ...

ZDNet

ZDNet
Mon, 06 Apr 2015 10:34:44 -0700

Like the Snapdragon 810, the Apple A8 (iPhone 6 and iPhone 6 Plus) and A8X (iPad Air 2) are made by TSMC on its 20nm planar process. But Samsung may have won back much of Apple's business on the A9 because of its lead on FinFETs. More Surface 3.

EE Times

EE Times
Tue, 24 Mar 2015 08:33:41 -0700

TORONTO – TLC NAND has made inroads into consumer devices and some data centers, but there is still plenty of room to improve MLC NAND: Micron recently introduced FortisFlash, aimed at balancing endurance and performance for enterprise storage ...
 
ElectronicsWeekly.com
Thu, 26 Mar 2015 04:12:15 -0700

The only people making 3D NAND are Samsung, and they can only make a 128TLC device on a 32-layer stack, which is the same density as it's getting on its best part on a planar process (19nm) at no better cost. Obviously no one at Samsung is saying, but ...
 
ElectroIQ (blog)
Mon, 06 Apr 2015 11:45:00 -0700

If the 7420 was a straight shrink of the 5433, we'd expect it to be 55 – 60 mm^2, but the back-end metallization stack is reported to be similar to the 20-nm planar process, so a full 50% shrink is unlikely (and the analog regions never shrink as well ...

PC Perspectives

PC Perspectives
Thu, 26 Mar 2015 11:21:47 -0700

... This excessive error correction on TLC as opposed to MLC, and SLC, and the issues around slower read and write speeds, and long term data retention in the TLC memory cells as the planar cell size was reduced in the newer planar process nodes.
 
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Sat, 11 Apr 2015 00:45:08 -0700

Graphene just got easier to see. The one-atom-thick material which is the favourite substance to succeed silicon for making electronic components, can now be identified quickly and cheaply instead of by the lengthy and expensive methods of either ...
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