digplanet beta 1: Athena
Share digplanet:

Agriculture

Applied sciences

Arts

Belief

Business

Chronology

Culture

Education

Environment

Geography

Health

History

Humanities

Language

Law

Life

Mathematics

Nature

People

Politics

Science

Society

Technology

The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography

See also[edit]

References[edit]

  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).

Other[edit]


Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Planar_process — Please support Wikipedia.
This page uses Creative Commons Licensed content from Wikipedia. A portion of the proceeds from advertising on Digplanet goes to supporting Wikipedia.

179 news items

AnandTech

AnandTech
Fri, 22 Apr 2016 02:03:22 -0700

Even if 20nm is technically the last planar process, it's not all that attractive compared to 28nm due to cost, DIBL leakage, and sheer heat density. Samsung's 28FDS process has been in mass production for some time now as a higher-end node designed to ...

KitGuru

KitGuru
Wed, 29 Apr 2015 23:46:01 -0700

United Microelectronics Corp., the world's second largest contract maker of semiconductors, said that it would not offer 20nm planar fabrication process, but will jump directly to 16nm FinFET manufacturing technology. Skipping the node will help the ...

Softpedia

Softpedia
Sat, 19 Oct 2013 00:17:28 -0700

AMD may not have its own foundry, exactly, but it did essentially found Globalfoundries. Thus, it has some control over when and how its process technologies advance. Over the next 2 quarters, the 14nm FinFET and 20nm planar process technologies should ...
 
EE Times
Wed, 21 Sep 2011 07:03:23 -0700

The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density. Paper 15.1, Bulk ...

Newsweek

Newsweek
Sun, 20 Mar 2016 08:37:56 -0700

“Jean Hoerni invented a way of making integrated circuits, called the planar process, which absolutely revolutionized the building of semiconductors,” says Laws. “It turned it from a handcrafted, one-at-a-time operation into a mass production operation ...

ExtremeTech

ExtremeTech
Thu, 06 Aug 2015 12:02:35 -0700

We suspect that at least some manufacturers will take this road, while others will try to combine their cutting edge planar process technology with die stacking as quickly as possible in order to reap the maximum amount of cost savings and capacity boosts.

Forbes

Forbes
Mon, 22 Feb 2016 16:04:09 -0800

Which is why the older 2D/planar process nodes are still popular for cost-sensitive embedded and IoT devices. The present leading-edge embedded process node is 28nm. It offers a nice balance between cost and power and is mature enough to be relatively ...

EE Times

EE Times
Fri, 05 Feb 2016 05:06:57 -0800

SAN FRANCISCO – Micron described a novel flash design that on paper beats the vertical NAND technology Samsung has been using to drive its leadership in non-volatile memory. The two gave competing presentations at this week's International ...
Loading

Oops, we seem to be having trouble contacting Twitter

Support Wikipedia

A portion of the proceeds from advertising on Digplanet goes to supporting Wikipedia. Please add your support for Wikipedia!

Searchlight Group

Digplanet also receives support from Searchlight Group. Visit Searchlight