The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.
The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.
The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.
Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography. Some researchers use even higher-energy extreme ultraviolet lithography
Building the Future: The Planar Integrated Circuit
[Recorded: May 8, 2009] The solid circuits built originally by Jack Kilby established that all the components required to make general-purpose electronic circuits could be fabricated using...
Understanding The FinFet Semiconductor Process
This video has been updated and the new version can be viewed at the link below. http://youtu.be/YYDNG4crRCs Threshold Systems provides consulting services to semiconductor manufacturers,...
Fairchild Briefing on Integrated Circuits
[Recorded: October, 1967] This half hour color promotional/educational film on the integrated circuit was produced and sponsored by Fairchild Semiconductor Corporation and first shown on television...
Planar Technology. D-Pak Features
Planar Technology. D-Pak Features. The planar technology combines a number of process operations to fabricate semiconductor devices with p-n junctions. P-n boundaries...
The assembly process uses planar fabrication methods to make assembly fast and easy
The assembly process uses planar fabrication methods to make assembly fast and easy. Fabrication requires a solid ink printer, a ferric chloride etch tank, a laser machining system, and a board...
Introduction to Planar Mapping (Projection) with Autodesk Maya
Level: Beginner This video demos the basics of UV mapping with planar projection technique, whereby it is a process about how to wrap a 2d texture image onto a 3d object.
Tutorial: Digital makeup with mocha Pro planar tracking
Adding digital makeup and improving skin wrinkes & blemishes can be a timely process. In this video tutorial, Imagineer Systems Product Manager, Martin Brennand shows how mocha Pro's planar...
Build technique for 5.8GHz CP antennas (Cloverleaf or Skew-Planar Wheel)
This is the way I have been building my Cloverleaf and Skew-Planar antennas. I have no idea if this is actually a good way of building them. What I knwo is that these antennas clearly outperform...
The Legacy of Fairchild Semiconductor
[Recorded Oct 5, 2007] Founded in September 1957 in Palo Alto, California by eight young engineers and scientists from Shockley Semiconductor Laboratories, Fairchild Semiconductor Corporation...
Moments and Center of Mass 4 - Integral Formula for Planar Lamina
Calculus: We derive the integral formula for the moments of a planar lamina using the limit process for integration.
Fri, 10 Apr 2015 06:30:00 -0700
Global Foundries and Samsung (OTC:SSNLF) have begun ramping their own 14nm FinFET process for customers as of earlier this month, and TSMC debuted its 20nm planar process back in September with Apple's (NASDAQ:AAPL) iPhone 6. The fabs may ...
Fri, 10 Apr 2015 07:48:45 -0700
At that time, advances were adopted quickly and widely – Jean Hoerni's planar process revolutionised the IC industry. By 1964, 75% of the semiconductor industry were using the planar process, but fewer than ten companies had actually licensed it ...
Mon, 06 Apr 2015 10:34:44 -0700
Like the Snapdragon 810, the Apple A8 (iPhone 6 and iPhone 6 Plus) and A8X (iPad Air 2) are made by TSMC on its 20nm planar process. But Samsung may have won back much of Apple's business on the A9 because of its lead on FinFETs. More Surface 3.
Tue, 24 Mar 2015 08:33:41 -0700
TORONTO – TLC NAND has made inroads into consumer devices and some data centers, but there is still plenty of room to improve MLC NAND: Micron recently introduced FortisFlash, aimed at balancing endurance and performance for enterprise storage ...
Thu, 26 Mar 2015 04:12:15 -0700
The only people making 3D NAND are Samsung, and they can only make a 128TLC device on a 32-layer stack, which is the same density as it's getting on its best part on a planar process (19nm) at no better cost. Obviously no one at Samsung is saying, but ...
Mon, 06 Apr 2015 11:45:00 -0700
If the 7420 was a straight shrink of the 5433, we'd expect it to be 55 – 60 mm^2, but the back-end metallization stack is reported to be similar to the 20-nm planar process, so a full 50% shrink is unlikely (and the analog regions never shrink as well ...
Thu, 26 Mar 2015 11:21:47 -0700
... This excessive error correction on TLC as opposed to MLC, and SLC, and the issues around slower read and write speeds, and long term data retention in the TLC memory cells as the planar cell size was reduced in the newer planar process nodes.
Sat, 11 Apr 2015 00:45:08 -0700
Graphene just got easier to see. The one-atom-thick material which is the favourite substance to succeed silicon for making electronic components, can now be identified quickly and cheaply instead of by the lengthy and expensive methods of either ...
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