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The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography


  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).


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107 news items

Tue, 20 Jan 2015 06:28:08 -0800

The only people making 3D NAND are Samsung, and they can only make a 128TLC device on a 32-layer stack, which is the 2nd gen part, and is the same density as it's getting on its best part on a planar process (19nm) at no better cost. Despite these ...
Seeking Alpha
Thu, 15 Jan 2015 10:45:00 -0800

Notably, Samsung has never maintained that it is more economical to make than its 19nm planar process. It is against this backdrop that Scott DeBoer's (Micron VP of R&D) announcement at this summer's Analyst Conference that the new 32L device would ...
Tue, 30 Dec 2014 22:32:35 -0800

In 1962 John Hall met semiconductor pioneer Jean Hoerni, one of the eight founders of Fairchild and the inventor of the planar process, the basis of today's microchip technology. Hoerni invited Hall to develop ICs at Union Carbide. This was Hall's ...
EE Times
Wed, 21 Sep 2011 07:03:23 -0700

The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density. Paper 15.1, Bulk ...
Seeking Alpha
Mon, 01 Dec 2014 12:55:10 -0800

In the current planar process node generation, the capacity is 128GB (MLC). Depending on the size of the die, the wafer contains more or less of these die. Once we know the number of die, we can multiply that number by the capacity of that die and then ...


Thu, 02 Oct 2014 13:12:03 -0700

The two companies said that 14nm chips will be up to 15 percent smaller than those manufactured on a 20nm planar process, while TSMC's 16nm FinFET process will deliver no scaling benefit over 20nm. The move also provides a second source for 14nm ...
PC Magazine
Tue, 23 Dec 2014 11:37:12 -0800

Those eight moved on to form what would become Fairchild Semiconductor, and while there Noyce, Moore, and the under-appreciated Jean Hoerni (one of the original eight) created the planar process for semiconductor manufacturing, which has been the ...
Thu, 23 Oct 2014 02:35:40 -0700

The thing that really stands out here about the Tegra K1 though, is the fact that it manages to match and even best Apple's A8X in terms of real life performance with a chip which is based on the older, cheaper and slower 28nm planar process, and with ...

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