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The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography

References[edit]

  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).

Other[edit]


Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Planar_process — Please support Wikipedia.
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113 news items

ExtremeTech

ExtremeTech
Thu, 06 Aug 2015 12:02:35 -0700

We suspect that at least some manufacturers will take this road, while others will try to combine their cutting edge planar process technology with die stacking as quickly as possible in order to reap the maximum amount of cost savings and capacity boosts.

KitGuru

KitGuru
Wed, 29 Apr 2015 23:46:01 -0700

United Microelectronics Corp., the world's second largest contract maker of semiconductors, said that it would not offer 20nm planar fabrication process, but will jump directly to 16nm FinFET manufacturing technology. Skipping the node will help the ...

Tom's Hardware

Tom's Hardware
Wed, 05 Aug 2015 10:01:13 -0700

Samsung ships 16nm 2D planar NAND that competes with Flash Forward's 15nm planar process node. Similarly, IMFT has 16nm planar NAND but has been reluctant to specify the process node for next generation 3D flash. The secret sauce makes it difficult ...
 
Softpedia
Sat, 19 Oct 2013 00:17:28 -0700

AMD may not have its own foundry, exactly, but it did essentially found Globalfoundries. Thus, it has some control over when and how its process technologies advance. Over the next 2 quarters, the 14nm FinFET and 20nm planar process technologies should ...
 
EE Times
Wed, 21 Sep 2011 07:03:23 -0700

The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density. Paper 15.1, Bulk ...

ExtremeTech

ExtremeTech
Tue, 28 Apr 2015 07:34:46 -0700

There's been a debate brewing over the last few days over Qualcomm's Snapdragon 810, its performance characteristics, and whether the SoC was harmed by moving to 20nm at TSMC. We've been investigating this issue for the past few days, and reached ...
 
PC Magazine
Thu, 23 Jul 2015 08:49:40 -0700

GlobalFoundries claims that with this approach it can produce chips that deliver better performance and lower power than the commonly-used 28nm planar process at a comparable cost (and much lower cost than 14nm FinFETs, which require many more ...
 
HPCwire
Mon, 22 Jun 2015 06:47:22 -0700

Advanced Fabrication: The new processors comprise over 128,000 Josephson junctions (tunnel junctions with superconducting electrodes) in a 6-metal layer planar process with 0.25µm features, believed to be the most complex superconductor integrated ...
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