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The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography

References[edit]

  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).

Other[edit]


Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Planar_process — Please support Wikipedia.
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4 news items

ZDNet

ZDNet
Thu, 02 Oct 2014 13:12:03 -0700

The two companies said that 14nm chips will be up to 15 percent smaller than those manufactured on a 20nm planar process, while TSMC's 16nm FinFET process will deliver no scaling benefit over 20nm. The move also provides a second source for 14nm ...

Tom's Hardware

Tom's Hardware
Tue, 30 Sep 2014 14:27:00 -0700

Considering ARM chips stood on their own on the 28nm planar process against Intel Atom's 22nm Tri-gate, it should be much harder for Atom to remain competitive against 16FF ARM chips, even when built on Intel's 14nm process. So far, the first two major ...

ExtremeTech

ExtremeTech
Tue, 07 Oct 2014 06:50:04 -0700

Also you are comparing the 28nm planar process with which the nVidia Tegra K1 is built, and has been around for at least 3 years with the 14nm FinFET process which Intel hasn't produced in quantity yet. Intels 14nm production schedule is roughly in ...
 
Times of India
Sun, 28 Sep 2014 05:26:49 -0700

According to Apple the A8, which is manufactured by TSMC on a 20nm planar process, has about 2B transistors on a 89mm2 die. According to Intel the Core M manufactured on a 14nm FinFET process has about 1.3B transistors on an 82mm2 die. dhiraj dilip ...
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