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The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography


  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).


Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Planar_process — Please support Wikipedia.
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143 news items


Wed, 29 Apr 2015 23:46:01 -0700

United Microelectronics Corp., the world's second largest contract maker of semiconductors, said that it would not offer 20nm planar fabrication process, but will jump directly to 16nm FinFET manufacturing technology. Skipping the node will help the ...
Sat, 19 Oct 2013 00:17:28 -0700

AMD may not have its own foundry, exactly, but it did essentially found Globalfoundries. Thus, it has some control over when and how its process technologies advance. Over the next 2 quarters, the 14nm FinFET and 20nm planar process technologies should ...
EE Journal
Tue, 24 Feb 2015 08:58:32 -0800

That means that these families are based on TSMC's 16nm FinFET process - rather than the 20nm planar process that the current “UltraScale” devices use. And, since we're on the topic of underlying fabrication process and FinFETs, let's get that part of ...


Mon, 06 Apr 2015 10:34:44 -0700

Like the Snapdragon 810, the Apple A8 (iPhone 6 and iPhone 6 Plus) and A8X (iPad Air 2) are made by TSMC on its 20nm planar process. But Samsung may have won back much of Apple's business on the A9 because of its lead on FinFETs. More Surface 3.

PC Perspectives

PC Perspectives
Thu, 26 Mar 2015 11:21:47 -0700

... This excessive error correction on TLC as opposed to MLC, and SLC, and the issues around slower read and write speeds, and long term data retention in the TLC memory cells as the planar cell size was reduced in the newer planar process nodes.


Sun, 15 Feb 2015 23:28:33 -0800

Samsung has announced the industry first chip based on 14nm 3D FinFET processor. This is a marked improvement over the 20nm planar process used to manufacture the current generation Exynos 7 processor. According to Samsung, the new Exynos 7 ...
Seeking Alpha
Fri, 10 Apr 2015 06:30:00 -0700

Global Foundries and Samsung (OTC:SSNLF) have begun ramping their own 14nm FinFET process for customers as of earlier this month, and TSMC debuted its 20nm planar process back in September with Apple's (NASDAQ:AAPL) iPhone 6. The fabs may ...
EE Times
Wed, 21 Sep 2011 07:03:23 -0700

The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density. Paper 15.1, Bulk ...

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