The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.
The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.
The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.
Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography. Some researchers use even higher-energy extreme ultraviolet lithography
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[Recorded: October, 1967] This half hour color promotional/educational film on the integrated circuit was produced and sponsored by Fairchild Semiconductor C...
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Mon, 01 Dec 2014 12:55:10 -0800
In the current planar process node generation, the capacity is 128GB (MLC). Depending on the size of the die, the wafer contains more or less of these die. Once we know the number of die, we can multiply that number by the capacity of that die and then ...
Mon, 08 Dec 2014 09:47:09 -0800
The metal stack is stated to be the same as the 20-nm planar process with a 1x pitch of 64 nm. Paper 3.2 is from Avago, discussing Analog Circuit and Device Interaction in High-Speed SerDes Design in 16nm FinFet Process, and Renesas presents 3.3, ...
Wed, 21 Sep 2011 07:03:23 -0700
The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density. Paper 15.1, Bulk ...
Thu, 02 Oct 2014 13:12:03 -0700
The two companies said that 14nm chips will be up to 15 percent smaller than those manufactured on a 20nm planar process, while TSMC's 16nm FinFET process will deliver no scaling benefit over 20nm. The move also provides a second source for 14nm ...
Tue, 14 Oct 2014 18:53:10 -0700
But would the Honorable Mention go to the inventor or the optimizer. In the case of Jack Kilby's invention and demonstration of the integrated circuit, I suspect that both he and Robert Noyce would have been recognized equally. Noyce's planar process ...
Thu, 16 Oct 2014 09:12:02 -0700
Tegra K1 (Denver) and Nexus 9 benchmarked - read the full text The Tegra K1 comes in two versions – 32-bit and 64-bit – but they are more different than NVIDIA's naming scheme suggest. The one we've tested in the Xiaomi MiPad and that powers the ...
Thu, 30 Oct 2014 08:42:18 -0700
When Intel announced the details on its 14nm process last year, it raised eyebrows in some circles by claiming some extremely aggressive scaling figures. Put simply, Intel stated that it would deliver a better 14nm process with superior characteristics ...
Thu, 23 Oct 2014 02:35:40 -0700
The thing that really stands out here about the Tegra K1 though, is the fact that it manages to match and even best Apple's A8X in terms of real life performance with a chip which is based on the older, cheaper and slower 28nm planar process, and with ...
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