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The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact bias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography

References[edit]

  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).

Other[edit]


Original courtesy of Wikipedia: http://en.wikipedia.org/wiki/Planar_process — Please support Wikipedia.
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101 news items

ExtremeTech

ExtremeTech
Thu, 30 Oct 2014 08:42:18 -0700

When Intel announced the details on its 14nm process last year, it raised eyebrows in some circles by claiming some extremely aggressive scaling figures. Put simply, Intel stated that it would deliver a better 14nm process with superior characteristics ...
 
EE Times
Wed, 21 Sep 2011 07:03:23 -0700

The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density. Paper 15.1, Bulk ...

ZDNet

ZDNet
Thu, 02 Oct 2014 13:12:03 -0700

The two companies said that 14nm chips will be up to 15 percent smaller than those manufactured on a 20nm planar process, while TSMC's 16nm FinFET process will deliver no scaling benefit over 20nm. The move also provides a second source for 14nm ...
 
GSMArena.com
Thu, 23 Oct 2014 02:35:40 -0700

The thing that really stands out here about the Tegra K1 though, is the fact that it manages to match and even best Apple's A8X in terms of real life performance with a chip which is based on the older, cheaper and slower 28nm planar process, and with ...
 
EE Times
Tue, 14 Oct 2014 18:53:10 -0700

But would the Honorable Mention go to the inventor or the optimizer. In the case of Jack Kilby's invention and demonstration of the integrated circuit, I suspect that both he and Robert Noyce would have been recognized equally. Noyce's planar process ...
 
GSMArena.com
Thu, 16 Oct 2014 09:12:02 -0700

Tegra K1 (Denver) and Nexus 9 benchmarked - read the full text The Tegra K1 comes in two versions – 32-bit and 64-bit – but they are more different than NVIDIA's naming scheme suggest. The one we've tested in the Xiaomi MiPad and that powers the ...

EE Journal

EE Journal
Thu, 25 Sep 2014 08:41:45 -0700

The move to from 28nm to 20nm, which should increase the number of die on a wafer, is proving difficult, although TSMC appears to have cracked it for a planar process to build the 60 million A8 processors they are supplying to Apple. FinFET, which is ...

ExtremeTech

ExtremeTech
Tue, 07 Oct 2014 06:50:04 -0700

Also you are comparing the 28nm planar process with which the nVidia Tegra K1 is built, and has been around for at least 3 years with the 14nm FinFET process which Intel hasn't produced in quantity yet. Intels 14nm production schedule is roughly in ...
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