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The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed[1][2] by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

Early versions of the planar process used a photolithography process using ordinary visible light. As of 2011, small features are typically made with 193 nm "deep" UV lithography.[3] Some researchers use even higher-energy extreme ultraviolet lithography


  1. ^ US 3025589  Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959
  2. ^ US 3064167  Hoerni, J. A.: "Semiconductor device" filed May 15, 1960
  3. ^ Shannon Hill. "UV Lithography: Taking Extreme Measures". National Institute of Standards and Technology (NIST).


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117 news items

PC Perspectives

PC Perspectives
Thu, 26 Mar 2015 11:21:47 -0700

... This excessive error correction on TLC as opposed to MLC, and SLC, and the issues around slower read and write speeds, and long term data retention in the TLC memory cells as the planar cell size was reduced in the newer planar process nodes.
Thu, 26 Mar 2015 04:10:21 -0700

The only people making 3D NAND are Samsung, and they can only make a 128TLC device on a 32-layer stack, which is the same density as it's getting on its best part on a planar process (19nm) at no better cost. Obviously no one at Samsung is saying, but ...

EE Times

EE Times
Tue, 24 Mar 2015 08:22:30 -0700

TORONTO – TLC NAND has made inroads into consumer devices and some data centers, but there is still plenty of room to improve MLC NAND: Micron recently introduced FortisFlash, aimed at balancing endurance and performance for enterprise storage ...


Sun, 15 Feb 2015 23:28:33 -0800

Samsung has announced the industry first chip based on 14nm 3D FinFET processor. This is a marked improvement over the 20nm planar process used to manufacture the current generation Exynos 7 processor. According to Samsung, the new Exynos 7 ...


Thu, 02 Oct 2014 13:12:03 -0700

The two companies said that 14nm chips will be up to 15 percent smaller than those manufactured on a 20nm planar process, while TSMC's 16nm FinFET process will deliver no scaling benefit over 20nm. The move also provides a second source for 14nm ...
EE Times
Wed, 21 Sep 2011 07:03:23 -0700

The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density. Paper 15.1, Bulk ...
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Mon, 01 Dec 2014 12:55:10 -0800

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Wed, 18 Feb 2015 12:28:55 -0800

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